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| general description the ds32b35/ds32c35 accurate real-time clocks (rtc) are clock/calendars that include an integrated temperature-compensated crystal oscillator (tcxo), crystal, and a bank of nonvolatile memory (fram) in a single package. the nonvolatile memory is available in two densities: 2048 x 8 and 8192 x 8 bits. the integra- tion of the crystal resonator enhances the long-term accuracy of the devices as well as reduces the piece part count in a manufacturing line. the devices operate as a slave device on an i 2 c serial interface, and are available in both commercial and industrial temperature ranges in a 300-mil, 20-pin so package. the clock/date provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the ds32b35/ds32c35 include a bank of nonvolatile memory that does not require a backup energy source to maintain memory contents. in addition, there are no read or write cycle limitations. the memory array can be accessed at maximum cycle rates for the life of the product with no wear-out mechanisms. other device features include two time-of-day alarms, a selectable output that provides either an interrupt or programmable square wave, and a calibrated 32.768khz square-wave output. a reset input/output pin provides a power-on reset for other devices. additionally, the reset pin is monitored as a pushbutton input for generating a reset externally. a precision temperature-compensated voltage refer- ence and comparator circuit monitor the status of v cc to detect power failures, to provide a reset output, and to automatically switch to the backup supply for the rtc/tcxo when necessary. additionally, the rst pin is monitored as a pushbutton input for generating a reset externally. applications servers utility power meters telematics gps features ? integrated 32.768khz crystal ? fast (400khz) i 2 c interface ? rtc counts seconds, minutes, hours, day, date, month, and year with leap year compensation valid up to 2100 ? rtc accuracy 2ppm from 0c to +40c ? rtc accuracy 3.5ppm from -40c to 0c and +40c to +85c ? nonvolatile memory with 10 years of guaranteed backup time and write protection ? two available densities of nonvolatile memory 2048 bytes (ds32b35) 8192 bytes (ds32c35) ? no cycle limitations on memory ? power-switching circuit selects between main power and battery backup for the rtc ? programmable square wave with frequency of 32.768khz, 8.192khz, 4.096khz, or 1hz ? two time-of-day alarms ? reset output/pushbutton reset (debounced) input ? programmable output provides interrupt or square wave ? calibrated 32.768khz open-drain output ? temp sensor with 3c accuracy ? 3.3v operating voltage ? commercial and industrial temperature ranges ? 300-mil, 20-pin so package ? underwriters laboratories (ul) recognized ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram ______________________________________________ maxim integrated products 1 19-5340; rev 3; 7/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. typical operating circuit, pin configuration, and selector guide appear at end of data sheet. ordering information part temp range pin-package ds32b35 -33# 0c to +70c 20 so ds32b35-33ind# -40c to +85c 20 so ds32c35 -33# 0c to +70c 20 so DS32C35-33IND# -40c to +85c 20 so #denotes a rohs-compliant device that may include lead that is exempt under rohs requirements. the lead finish is jesd97 category e3, and is compatible with both lead-based and lead- free soldering processes. a "#" anywhere on the top mark denotes a rohs-compliant device.
ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +85?, unless otherwise noted.) (notes 2, 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on any pin relative to ground......-0.3v to +5.0v operating temperature range ..........................-40? to +85? junction temperature ......................................................+125? storage temperature range ...............................-40? to +85? junction-to-ambient thermal resistance ( ja ) (note 1)....55?/w junction-to-case thermal resistance ( jc ) (note 1) ......24?/w lead temperature (soldering, 10s) .................................+260? soldering temperature (reflow, 2x max)..........................+260? (see the handling, pc board layout, and assembly section.) parameter symbol conditions min typ max units supply voltage v cc 2.70 3.3 3.63 v battery voltage v bat (note 4) 2.3 3.0 3.6 v input high voltage v ih (note 5) 0.7 x v cc v cc + 0.3 v input low voltage v il -0.3 +0.3 x v cc v electrical characteristics ( v cc = 2.7v to 3.63v , t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units accessing rtc 260 active supply current i cca v cc = 3.63v, scl = 400khz (note 6) accessing fram memory 260 a standby supply current i ccs v cc = 3.63v, scl = 0khz, 32khz on, sqw off (note 6) 110 a temperature conversion current i tc v cc = 3.65v, scl = 0khz, 32khz on, sqw off 575 a power-fail voltage v pf 2.45 2.575 2.70 v logic 0 output 32khz, int /sqw, sda v ol i ol = 3ma 0.4 v logic 0 output rst v ol i ol = 1ma 0.4 v output leakage current 32khz, int /sqw, sda i leak output high impedance -1 +1 a input leakage scl i li -1 +1 a rst i/o leakage i ol rst high impedance (note 7) -200 +10 a v in = v il(max) 50 k wp input resistance r in v in = v ih(min) 1 m note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram _____________________________________________________________________ 3 electrical characteristics (continued) ( v cc = 2.7v to 3.63v , t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units v bat leakage current (v cc active) i batlkg 25 100 na output frequency f out v cc = 3.3v or v bat = 3.3v 32.768 khz -40c to 0c -3.5 +3.5 0c to +40c -2 +2 frequency stability vs. temperature f/f out v cc = 3.3v or v bat = 3.3v -40c to +85c -3.5 +3.5 ppm frequency stability vs. voltage f/v 1 ppm/v -40c 0.7 +25c 0.1 +70c 0.4 frequency sensitivity per lsb f/lsb specified at: +85c 0.8 ppm temperature sensor accuracy temp v cc = 3.3v or v bat = 3.3v -3 +3 c temperature conversion time t conv 125 200 ms electrical characteristics ( v cc = 0v, v bat = 2.3v to 3.6v , t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units active battery current i bata eosc = 0, bbsqw = 0, scl = 400khz (note 5) v bat = 3.6v 70 a timekeeping battery current i batt eosc = 0, bbsqw = 0, en32khz = 1, scl = sda = 0v or scl = sda = v bat (note 6) v bat = 3.6v 0.84 3.0 a temperature conversion current i battc eosc = 0, bbsqw = 0, scl = sda = 0v or scl = sda = v bat v bat = 3.6v 575 a data-retention current (rtc/tcxo registers) i batdr eosc = 1, scl = sda = 0v, +25c 100 na ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 4 _____________________________________________________________________ ac electrical characteristics (v cc = 2.7v to 3.63v, t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units fast mode 100 400 scl clock frequency f scl standard mode 0 100 khz fast mode 1.3 bus free time between stop and start conditions t buf standard mode 4.7 s fast mode 0.6 hold time (repeated) start condition (note 8) t hd:sta standard mode 4.0 s fast mode 1.3 low period of scl clock t low standard mode 4.7 s fast mode 0.6 high period of scl clock t high standard mode 4.0 s fast mode 0 0.9 data hold time (notes 9, 10) t hd:dat standard mode 0 s fast mode 100 data setup time (note 11) t su:dat standard mode 250 ns fast mode 0.6 setup time for repeated start condition t su:sta standard mode 4.7 s fast mode 300 rise time of both sda and scl signals (note 12) t r standard mode 20 + 0.1c b 1000 ns fast mode 300 fall time of both sda and scl signals (note 12) t f standard mode 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.0 s capacitive load for each bus line (note 12) c b 400 pf 10 i/o capacitance int /sqw, 32khz, scl, sda c i/o outputs = high impedance 18 pf pushbutton debounce pb db (see the pushbutton reset timing diagram) 250 ms reset active time t rst 250 ms oscillator stop flag (osf) delay t osf (note 13) 100 ms fram data retention t dr 10 years ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram _____________________________________________________________________ 5 power-switch characteristics (t a = -40? to +85?, note 2, see the power-switch timing diagram.) parameter symbol conditions min typ max units v cc fall time; v pf(max) to v pf(min) t vccf 300 s v cc rise time; v pf(min) to v pf(max) t vccr 0 s recovery at power-up t rec (note 14) 300 ms note 2: limits at -40? are guaranteed by design and not production tested. note 3: all voltages are referenced to ground. note 4: to minimize current drain on v bat when the internal supply is switched to v bat , the v ih minimum must be higher than v bat - 0.6v. otherwise, there is significant current drain due to the input stage at the scl and sda pins. note 5: the pullup resistor voltage on the 32khz and int /sqw pins can be up to 5.5v maximum regardless of the voltage on v cc . note 6: current is the averaged input current, which includes the temperature conversion current. note 7: the rst pin has an internal 50k (nominal) pullup resistor to v cc . note 8: after this period, the first clock pulse is generated. note 9: a device must internally provide a hold time of at least 300ns for the sda signal (referred to as the v ih(min) of the scl sig- nal) to bridge the undefined region of the falling edge of scl. note 10: the maximum t hd:dat needs only to be met if the device does not stretch the low period (t low ) of the scl signal. note 11: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 12: c b ?otal capacitance of one bus line in pf. note 13: the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set over the voltage range of 0.0v v cc v cc(max) and 2.0v v bat 3.6v. note 14: this delay applies only if the oscillator is enabled and running. if the eosc bit is a 1, t rec is bypassed and rst immedi- ately goes high. the state of rst does not affect the i 2 c interface, rtc, tcxo, or fram operation. warning: negative undershoots below -0.3v while the part is in battery-backed mode may cause loss of data. ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 6 _____________________________________________________________________ pushbutton reset timing t rst pb db rst power-switch timing v cc t vccf t vccr t rec v pf(max) v pf v pf v pf(min) rst ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram _____________________________________________________________________ 7 supply current vs. temperature ds32x35 toc03 temperature ( c) i bat ( a) 60 35 10 -15 0.7 0.8 0.9 1.0 0.6 -40 85 v cc = 0v, en32khz = 1, bsy = 0, sda = scl = v bat or gnd frequency deviation vs. temperature vs. aging value ds32x35 toc04 temperature ( c) frequency deviation (ppm) 60 35 10 -15 -30 -20 -10 0 10 20 30 40 50 60 -40 -40 85 -128 0 -33 32 127 standby supply current vs. supply voltage ds32x35 toc01 v cc (v) i ccs ( a) 5.0 4.5 4.0 3.5 3.0 2.5 25 50 75 100 125 150 0 2.0 5.5 bsy = 0, sda = scl = v cc rst active supply current vs. supply voltage ds32x35 toc02 v bat (v) i bat ( a) 5.3 4.3 3.3 0.7 0.8 0.9 1.0 1.1 1.2 0.6 2.3 v cc = 0v, bsy = 0, sda = scl = v bat or v cc en32khz = 1 en32khz = 0 typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 8 _____________________________________________________________________ block diagram n n n rst v cc 32khz int/sqw clock and calendar registers user buffer (7 bytes) i 2 c interface and address register decode power control v cc wp scl v bat gnd scl sda temperature sensor fram control logic/ divider pushbutton reset; square-wave buffer; int/sqw control control and status registers oscillator and capacitor array x1 x2 ds32b35/ds32c35 ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram _____________________________________________________________________ 9 pin description pin name function 1 wp write protect. when wp is high, the entire fram memory array is write protected. when wp is low, all addresses can be written. this pin is internally pulled down. 2, 7C14 n.c. no connection. must be connected to ground. 3 32khz 32khz output. this open-drain pin requires an external pullup resistor. when enabled, the output operates on either power supply. it can be left open if not used. 4 v cc dc power pin for primary power supply. this pin should be decoupled using a 0.1f to 1.0f capacitor. 5 int /sqw active-low interrupt or square-wave output. this open-drain pin requires an external pullup resistor connected to v cc or another supply of 5.5v or less. it can be left open if not used. this multifunction pin is determined by the state of the intcn bit in the control register (0eh). when intcn is set to logic 0, this pin outputs a square wave and its frequency is determined by the rs2 and rs1 bits. when intcn is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the int /sqw pin (if the alarm is enabled). because the intcn bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled. 6 rst active-low reset. this pin is an open-drain input/output. it indicates the status of v cc relative to the v pf specification. as v cc falls below v pf , the rst pin is driven low. when v cc exceeds v pf , for t rst , the open-drain pulldown transistor is shut off, and the internal pullup resistor pulls the rst pin to v cc . the active- low, open-drain output is combined with a debounced pushbutton input function. this pin can be activated by a pushbutton reset request. it has an internal 50k nominal value pullup resistor to v cc . no external pullup resistors should be connected. if the eosc bit is 1, t rec is bypassed and rst immediately goes high. 15, 19 gnd ground. must be connected together to ground. 16 v bat backup power-supply input. when using the device with the v bat input as the primary power source, this pin should be decoupled using a 0.1f to 1.0f low-leakage capacitor. when using the device with the v bat input as the backup power source, the capacitor is not required. if v bat is not used, connect to ground. the devices are ul recognized to ensure against reverse charging when used with a primary lithium battery. go to www.maxim-ic.com/qa/info/ul . 17 sda serial data input/output. this pin is the data input/output for the i 2 c serial interface. this open-drain pin requires an external pullup resistor. 18, 20 scl serial clock input. these pins are the clock input for the i 2 c serial interface and are used to synchronize data movement on the serial interface. detailed description the ds32b35/ds32c35 accurate rtcs are clock/cal- endars that include an integrated tcxo, crystal, and a bank of nonvolatile memory (fram) in a single pack- age. the nonvolatile memory is available in two sizes: 2048 x 8 or 8192 x 8 bits. the integration of the crystal resonator enhances the long-term accuracy of the device as well as reduces the piece part count in a manufacturing line. the devices are available in both commercial and industrial temperature ranges and is offered in a 300-mil, 20-pin so package. the ds32b35/ds32c35 include a bank of nonvolatile memory that do not require a backup energy source to maintain the memory contents. in addition, there are no read or write cycle limitations. the memory array can be accessed at maximum cycle rates for the life of the product with no wear-out mechanisms. a precision temperature-compensated reference and comparator circuit monitors the status of v cc and auto- matically switches to the backup supply when neces- sary. other device features include two time-of-day alarms, a selectable output that provides either an interrupt or programmable square wave, and a calibrat- ed 32.768khz square-wave output. a reset input/output pin provides a power-on reset. additionally, the reset pin is monitored as a pushbutton input for generating a reset externally. the devices are accessed through an i 2 c serial interface. ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 10 ____________________________________________________________________ operation the block diagram shows the main elements of the ds32b35/ds32c35. the nine blocks can be grouped into six functional groups: tcxo, power control, pushbut- ton function, rtc, i 2 c interface, and fram. their opera- tions are described separately in the following sections. 32khz tcxo the temperature sensor, oscillator, and control logic form the tcxo. the controller reads the output of the on-chip temperature sensor and uses a lookup table to determine the capacitance required, adds the aging correction in the age register, and then sets the capacitance selection registers. new values, including changes to the age register, are loaded only when a change in the temperature value occurs, or when a user-initiated temperature conversion is completed. the temperature is read on initial application of v cc and once every 64 seconds afterwards while the device is powered by either v cc or v bat . power control this function is provided by a temperature-compensat- ed voltage reference and a comparator circuit that monitors the v cc level. when v cc is greater than v pf , the part is powered by v cc . when v cc is less than v pf but greater than v bat , the rtc is powered by v cc . if v cc is less than v pf and is less than v bat , the device is powered by v bat . see table 1. the rtc can be accessed when the device is powered by either v cc or v bat . the fram is only accessible when the device is powered by v cc . the fram must not be accessed when v cc < v cc(min) . to preserve the battery, the first time v bat is applied to the device, the oscillator will not start up until v cc exceeds v pf , or until a valid i 2 c address is written to the part. typical oscillator startup time is less than one second. approximately 2 seconds after v cc is applied, or a valid i 2 c address is written, the device makes a temperature measurement and applies the calculated correction to the oscillator. once the oscillator is run- ning, it continues to run as long as a valid power source is available (v cc or v bat ), and the device con- tinues to measure the temperature and correct the oscillator frequency every 64 seconds. on the first application of power (v cc ) or when a valid i 2 c address is written to the part (v bat ), the time and date registers are reset to 01/01/00 01 00:00:00 (mm/dd/yy dow hh:mm:ss). pushbutton reset function the device provides for a pushbutton switch to be con- nected to the rst output pin. when the device is not in a reset cycle, it continuously monitors the rst signal for a low going edge. if an edge transition is detected, the device debounces the switch by pulling rst low. after the internal timer has expired (pb db ), the device continues to monitor the rst line. if the line is still low, the device continuously monitors the line looking for a rising edge. upon detecting release, the device forces the rst pin low and holds it low for t rst . rst is also used to indicate a power-fail condition. when v cc is lower than v pf , an internal power-fail signal is generated, which forces the rst pin low. when v cc returns to a level above v pf , the rst pin is held low for t rec to allow the power supply to stabilize. if the oscilla- tor is not running (see the power control section) when v cc is applied, t rec is bypassed and rst immediately goes high. the state of rst does not affect the operation of the tcxo, i 2 c interface, fram, or rtc functions. real-time clock with the clock source from the tcxo, the rtc provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automati- cally adjusted for months with fewer than 31 days, includ- ing corrections for leap year. the clock operates in either the 24-hour or 12-hour format with an am /pm indicator. the clock provides two programmable time-of-day alarms and a programmable square-wave output. the int /sqw pin either generates an interrupt due to alarm condition or outputs a square-wave signal and the selection is controlled by the bit intcn. i 2 c interface the fram i 2 c interface is accessible whenever v cc is at a valid level. the rtc i 2 c interface is accessible whenever either v cc or v bat is at a valid level. if a microcontroller connected to the device resets because of a loss of v cc or other event, it is possible that the microcontroller and the rtc i 2 c communications could become unsynchronized, e.g., the microcontroller resets while reading data from the rtc. when the microcon- supply condition powered by fram access* rtc access v cc < v pf , v cc < v bat v bat no yes v cc < v pf , v cc > v bat v cc no yes v cc > v pf , v cc < v bat v cc yes yes v cc > v pf , v cc > v bat v cc yes yes table 1. device operation * read/write access is not inhibited by the device, but must not be done to avoid fram data errors. ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram ____________________________________________________________________ 11 troller resets, the rtc i 2 c interface may be placed into a known state by toggling scl until sda is observed to be at a high level. at that point the microcontroller should pull sda low while scl is high, generating a start condition. fram the serial fram memory is logically organized as a 2048 x 8 or 8192 x 8 memory array and is accessed using the i 2 c interface. functional operation of the fram is similar to serial eeproms with the major dif- ference being its superior performance on writes. the memory is read or written at the speed of the i 2 c inter- face. it is not necessary to poll the device for a ready condition during writes. due to the different memory densities, the i 2 c address- ing technique is different for each version of the device. see the i 2 c serial data bus section for details. warning: the fram does not inhibit reads or writes when v cc is below the minimum operating voltage. fram reads are destructive, that is, when a read is performed, the device internally writes the memory back to the original value. the fram must not be read or written when v cc is below the minimum operating voltage; otherwise, the memory cells may not be fully programmed, and the data may not be retained. rtc address map table 3 shows the rtc address map for the timekeep- ing registers. during a multibyte access, when the address pointer reaches the end of the register space, it wraps around to location 00h. on an i 2 c start or address pointer incrementing to location 00h, the cur- rent time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock continues to run. this eliminates the need to reread the registers in case the main registers update during a read. clock and calendar the time and calendar information is obtained by read- ing the appropriate register bytes. table 3 illustrates the rtc registers. the time and calendar data are set or ini- tialized by writing the appropriate register bytes. the con- tents of the time and calendar registers are in the binary-coded decimal (bcd) format. the device can be run in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am /pm bit with logic-high being pm. in the 24-hour mode, bit 5 is the 20-hour bit (20 to 23 hours). the century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. the day-of-week register increments at midnight. values that correspond to the day of week are user- defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, sec- ondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to the internal registers on any start and when the register pointer rolls over to zero. the time information is read from these secondary registers while the clock continues to run. this eliminates the need to reread the registers in case the main registers update during a read. the countdown chain is reset whenever the seconds register is written. write transfers occur on the acknowl- edge from the device. once the countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within 1 second. the 1hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer, provided that the oscil- lator is already running. device slave address ds32b35 1010 a 10 a 9 a 8 r ds32c35 1010 000r r = read/write select bit table 2. memory slave address ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 12 ____________________________________________________________________ table 3. rtc register map note: unless otherwise specified, the registers?state is not defined when power is first applied. bits indicated as 0 can be written to a 1 or 0, but always read back as 0. address bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) function range 00h 0 10 seconds seconds seconds 00C59 01h 0 10 minutes minutes minutes 00C59 am /pm 02h 0 12/ 24 20 hour 10 hour hour hours 1C12 + am /pm 00C23 03h 0 0 0 0 0 day day 1C7 04h 0 0 10 date date date 01C31 05h century 0 0 10 month month month/ century 01C12 + century 06h 10 year year year 00C99 07h a1m1 10 seconds seconds alarm 1 seconds 00C59 08h a1m2 10 minutes minutes alarm 1 minutes 00C59 am /pm 09h a1m3 12/ 24 20 hour 10 hour hour alarm 1 hours 1C12 + am /pm 00C23 day alarm 1 day 1C7 0ah a1m4 dy/ dt 10 date date alarm 1 date 1C31 0bh a2m2 10 minutes minutes alarm 2 minutes 00C59 am /pm 0ch a2m3 12/ 24 20 hour 10 hour hour alarm 2 hours 1C12 + am /pm 00C23 day alarm 2 day 1C7 0dh a2m4 dy/ dt 10 date date alarm 2 date 1C31 0eh eosc bbsqw conv rs2 rs1 intcn a2ie a1ie control 0fh osf 0 0 0 en32khz bsy a2f a1f control/status 10h sign data data data data data data data aging offset 11h sign data data data data data data data msb of temp 12h data data 0 0 0 0 0 0 lsb of temp ds32b35/ds32c35 alarms the ds32b35/ds32c35 contain two time-of-day/date alarms. alarm 1 can be set by writing to registers 07h to 0ah. alarm 2 can be set by writing to registers 0bh to 0dh. the alarms can be programmed (by the alarm enable and intcn bits of the control register) to acti- vate the int /sqw output on an alarm match condition. bit 7 of each of the time-of-day/date alarm registers are mask bits (table 4). when all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers match the corresponding values stored in the time-of-day/date alarm registers. the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 4 shows the possible settings. configurations not listed in the table will result in illogical operation. the dy/ dt bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. if dy/ dt is written to logic 0, the alarm is the result of a match with date of the month. if dy/ dt is written to logic 1, the alarm is the result of a match with day of the week. when the rtc register values match alarm register set- tings, the corresponding alarm flag (?1f? or (?2f? bit is set to logic 1. if the corresponding alarm interrupt enable (?1ie? or (?2ie? is also set to logic 1 and the intcn bit is set to logic 1, the alarm condition will acti- vate the int /sqw signal. table 4. alarm mask bits alarm 1 register mask bits (bit 7) dy/ dt a1m4 a1m3 a1m2 a1m1 alarm rate x 1 1 1 1 alarm once per second. x 1 1 1 0 alarm when seconds match. x 1 1 0 0 alarm when minutes and seconds match. x 1 0 0 0 alarm when hours, minutes, and seconds match. 0 0 0 0 0 alarm when date, hours, minutes, and seconds match. 1 0 0 0 0 alarm when day, hours, minutes, and seconds match. alarm 2 register mask bits (bit 7) dy/ dt a2m4 a2m3 a2m2 alarm rate x 1 1 1 alarm once per minute (00 seconds of every minute). x 1 1 0 alarm when minutes match. x 1 0 0 alarm when hours and minutes match. 0 0 0 0 alarm when date, hours, and minutes match. 1 0 0 0 alarm when day, hours, and minutes match. accurate i 2 c rtc with integrated tcxo/crystal/fram ____________________________________________________________________ 13 ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 14 ____________________________________________________________________ special-purpose registers control register (0eh) bit 7: enable oscillator ( eosc ). when set to logic 0, the oscillator is started. when set to logic 1, the oscilla- tor is stopped when the device switches to v bat . this bit is clear (logic 0) when power is first applied. when the device is powered by v cc , the oscillator is always on regardless of the status of the eosc bit. bit 6: battery-backed square-wave enable (bbsqw). when set to logic 1 with intcn = 0 and v cc ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 16 ____________________________________________________________________ note: unless otherwise specified, the state of the registers is not defined when power is first applied. note: unless otherwise specified, the state of the registers is not defined when power is first applied. temperature registers (11h?2h) temperature is represented as a 10-bit code with a res- olution of +0.25? and is accessible at location 11h and 12h. the temperature is encoded in two? comple- ment format. the upper 8 bits are at location 11h, and the lower 2 bits are in the upper nibble at location 12h. upon power reset, the registers are set to a default temperature of 0? and the controller starts a tempera- ture conversion. new temperature readings are stored in this register. fram address map during a multibyte access, the address pointer wraps around to location 00h when it reaches the end of the register space. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sign data data data data data data data temperature register (upper byte) (11h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data data 0 0 0 0 0 0 temperature register (lower byte) (12h) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 range 000h d7 d6 d5 d4 d3 d2 d1 d0 00Cff : : : : : : : : : : 7ffh d7 d6 d5 d4 d3 d2 d1 d0 00Cff ds32b35 fram register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 range 000h d7 d6 d5 d4 d3 d2 d1 d0 00Cff : : : : : : : : : : 1fffh d7 d6 d5 d4 d3 d2 d1 d0 00Cff ds32c35 fram register map ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram ____________________________________________________________________ 17 i 2 c serial data bus the ds32b35/ds32c35 support a bidirectional i 2 c bus and data transmission protocol (figure 1). a device that sends data onto the bus is defined as a transmitter, and a device receiving data is defined as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop condi- tions. the device operates as a slave on the i 2 c bus. connections to the bus are made through the scl input and open-drain sda i/o lines. within the bus specifica- tions, a standard mode (100khz maximum clock rate) and a fast mode (400khz maximum clock rate) are defined. the ds32b35/ds32c35 work in both modes. the following bus protocol has been defined (figure 2): data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. stop condition or repeated start condition repeated if more bytes are transfered ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3?7 figure 2. i 2 c data transfer overview sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 1. data transfer on i 2 c serial bus ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 18 ____________________________________________________________________ accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low, while the clock line is high, defines a start condition. stop data transfer: a change in the state of the data line from low to high, while the clock line is high, defines a stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and the stop conditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse, which is associ- ated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. depending upon the state of the r/ w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a num- ber of data bytes. the slave returns an acknowl- edge bit after each received byte. data is transferred with the most significant bit (msb) first. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge is returned. the master device generates all the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. data is transferred with the most significant bit (msb) first. the ds32b35/ds32c35 can operate in the following two modes: 1) slave receiver mode (ds32b35/ds32c35 write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit (see figures 3, 5, and 7). the slave address byte is the first byte received after the mas- ter generates the start condition. the slave address byte contains one of the 7-bit device addresses. the slave address is 1101000 for the rtc. for the ds32b35 fram, the first four bits are 1010, and the next three bits select one of eight blocks of data (see table 2). for the ds32c35 fram, the first seven bits are 1010000. each slave address is followed by the direction bit (r/ w ), which is zero for a write. after receiving and decoding the slave address byte, the device outputs an acknowl- edge on the sda line. after the device acknowl- edges the slave address and write bit, the master transmits a register address to the device. for the ds32c35, the master transmits two bytes for the register address information. this sets the register pointer on the device. after setting the register address, the master then transmits zero or more bytes of data with the device acknowledging each byte received. the master generates a stop condi- tion to terminate the data write. 2) slave transmitter mode (ds32b35/ds32c35 read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. the device transmits serial data on sda while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer (see figure 4). the slave address byte is the first byte received after the mas- ter generates the start condition. the slave address byte contains one of the 7-bit device addresses. the slave address is 1101000 for the rtc. for the ds32b35 fram, the first four bits are 1010, and the next three bits select one of eight blocks of data (see table 2). each slave address is followed by the direction bit (r/ w ), which is one for a read. after receiving and decoding the slave address byte, the device outputs an acknowledge on the sda line. the device then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. the device must receive a "not acknowledge" to end a read. the register pointer can be set prior to a data read by initiating a slave receiver mode sequence, with no data bytes transmitted after the register address data. ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram ____________________________________________________________________ 19 ... a xxxxxxxx a 1101000 s 0 xxxxxxxx a xxxxxxxx a xxxxxxxx a p ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram 20 ____________________________________________________________________ s - start a - acknowledge p - stop a - not acknowledge r/w - read/write or direction bit address = d1h a xxxxxxxx a s 1 xxxxxxxx a xxxxxxxx a xxxxxxxx a p ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram ____________________________________________________________________ 21 chip information substrate connected to ground process: cmos 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 scl gnd scl sda v cc 32khz n.c. wp top view v bat gnd n.c. n.c. n.c. n.c. rst int/sqw 12 11 9 10 n.c. n.c. n.c. n.c. so ds32b35/ ds32c35 pin configuration package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ds32b35/ ds32c35 v cc scl r pu r pu = t r /c b r pu int/sqw 32khz v bat pushbutton reset sda rst n.c. n.c. n.c. n.c. n.c. v cc v cc gnd v cc cpu n.c. gnd n.c. n.c. n.c. scl wp typical operating circuit selector guide part fram density top ? mark ds32b35 -33# 2k x 8 ds32b35 ds32b35-33ind# 2k x 8 ds32b35 ds32c35 -33# 8k x 8 ds32c35 DS32C35-33IND# 8k x 8 ds32c35 #denotes a rohs-compliant device that may include lead that is exempt under rohs requirements. the lead finish is jesd97 category e3, and is compatible with both lead-based and lead- free soldering processes. a "#" anywhere on the top mark denotes a rohs-compliant device. ? an ??anywhere on the top mark denotes an industrial grade device. package type package code outline no. land pattern no. 20 so w20#h2 21-0042 90-0108 ds32b35/ds32c35 accurate i 2 c rtc with integrated tcxo/crystal/fram maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 12/06 initial release changed data sheet title/references to ds32x35 with ds32b35/ds32c35 1C21 added text to the general description section about the clock/date operation 1 1 1/08 in table 3, changed 04h range from 00C31 to 01C31 12 updated the rtc descriptions in the general description and detailed description sections 1, 9 in the power-switch characteristics table, changed t rec max from 2ms to 200ms; added rst state information to note 13 3 in the typical operating characteristics section, replaced tocs 1 to 4 7 changed table 1 column headings; added information about the por state of the time and date registers to the end of the power control section 10 2 4/08 in the handling, pcb layout, and assembly section, added a limit to the number of passes through reflow 20 3 7/10 in the absolute maximum ratings section, added the theta-ja and theta-jc thermal resistances (changed from 73 c/w and 23 c/w to 55 c/w and 24 c/w), added note 1, and changed the soldering temperature to +260 c; changed the v bat pin function description in the pin description table; changed the 10-hour bit to 20-hour bit in the clock and calendar section and table 3; updated the bbsqw bit description in the control register (0eh) section; amended the v bat capacitor representation in the typical operating circuit ; added the land pattern no. to the package information table 2C5, 9, 11, 12, 14, 21 |
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